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參數(shù)資料
| 型號： | SMJ320C31KGDM40B |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 40 MHz, OTHER DSP, UUC132 |
| 封裝： | DIE |
| 文件頁數(shù)： | 27/59頁 |
| 文件大?。?/td> | 1236K |
| 代理商： | SMJ320C31KGDM40B |
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
timing for IACK (see Note 5 and Figure 25)
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
52
td(H1H-IACKL)
Delay time, H1 high to IACK low
9
7
6
ns
53
td(H1H-IACKH)
Delay time, H1 high to IACK high
9
7
6
ns
NOTE 5: IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle
(H1 rising) of the read phase of the IACK instruction. Because of pipeline conflicts, IACK remains low for one cycle even if the decode
phase of the IACK instruction is extended.
H3
H1
IACK
ADDR
Data
52
53
Fetch IACK
Instruction
IACK Data
Read
Decode IACK
Instruction
Figure 25. Timing for IACK
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相關代理商/技術參數(shù) |
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|---|---|
| SMJ320C40 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
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| SMJ320C40GFM50 | 制造商:Texas Instruments 功能描述:DSP Floating-Point 32-Bit 50MHz 25MIPS 325-Pin CPGA 制造商:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C40GFS60 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
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