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參數(shù)資料
| 型號： | SMJ320C31KGDM40B |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 40 MHz, OTHER DSP, UUC132 |
| 封裝： | DIE |
| 文件頁數(shù)： | 36/59頁 |
| 文件大小： | 1236K |
| 代理商： | SMJ320C31KGDM40B |
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
41
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
general-purpose I/O timing
Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The contents of the internal
control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The table, timing parameters for peripheral pin general-purpose I/O, defines peripheral pin general-purpose I/O
timing parameters.
timing requirements for peripheral pin general-purpose I/O (see Note 6 and Figure 29)
NO.
’C31-33
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
81
tsu(GPIO-H1L)
Setup time, general-purpose input
before H1 low
12
10
9
8
ns
82
th(H1L-GPIO)
Hold time, general-purpose input after
H1 low
0
ns
83
td(H1H-GPIO)
Delay time, general-purpose output
after H1 high
15
13
10
8
ns
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Peripheral
Pin
(see Note A)
H1
H3
83
81
82
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 29. Timing for Peripheral Pin General-Purpose I/O
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