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參數(shù)資料
| 型號： | SMJ320C31KGDM40B |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 40 MHz, OTHER DSP, UUC132 |
| 封裝： | DIE |
| 文件頁數(shù)： | 14/59頁 |
| 文件大?。?/td> | 1236K |
| 代理商： | SMJ320C31KGDM40B |
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
memory read/write timing
The following table defines memory read/write timing parameters for STRB.
timing parameters for memory (STRB = 0) read/write (see Figure 14 and Figure 15)
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
12
td(H1L-SL)
Delay time, H1 low to STRB low
0*
6
0*
5
0*
5
ns
13
td(H1L-SH)
Delay time, H1 low to STRB high
0*
6
0*
5
0*
5
ns
14
td(H1H-RWL)R
Delay time, H1 high to R/W low (read)
0*
9
0*
7
0*
6
ns
15
td(H1L-A)
Delay time, H1 low to A valid
0*
10
0*
10
0*
8
ns
16
tsu(D-H1L)R
Setup time, D before H1 low (read)
14
10
9
ns
17
th(H1L-D)R
Hold time, D after H1 low (read)
0
ns
18
tsu(RDY-H1H)
Setup time, RDY before H1 high
8
6
5
ns
19
th(H1H-RDY)
Hold time, RDY after H1 high
0
ns
20
td(H1H-RWH)W
Delay time, H1 high to R/W high (write)
9
7
6
ns
21
tv(H1L-D)W
Valid time, D after H1 low (write)
17
14
12
ns
22
th(H1H-D)W
Hold time, D after H1 high (write)
0
ns
23
td(H1H-A)W
Delay time, H1 high to A valid on back-to-back
write cycles (write)
15
14
10
ns
24
td(A-RDY)
Delay time, RDY from A valid
7*
6*
ns
See Figure 16 for address bus timing variation with load capacitance greater than typical load-circuit capacitance (CT = 80 pF).
* This parameter is not production tested.
12
14
15
13
16
17
19
18
H3
H1
R/W
A
D
RDY
STRB
24
NOTE A: STRB remains low during back-to-back read operations.
Figure 14. Timing for Memory (STRB = 0) Read
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