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參數(shù)資料
| 型號： | SMJ320C31KGDM40B |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 40 MHz, OTHER DSP, UUC132 |
| 封裝： | DIE |
| 文件頁數(shù)： | 24/59頁 |
| 文件大?。?/td> | 1236K |
| 代理商： | SMJ320C31KGDM40B |
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
30
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
RESET timing (continued)
CLKIN
H1
H3
38
39
42
45
46
49
48
41
40
43
RESET
(see Notes A and B)
IACK
Ten H1 Clock Cycles
D
(see Note C)
A
(see Note C)
Control Signals
(see Note D)
Asynchronous
Reset Signals
(see Note A)
44
47
SMJ320C31 R/W
(see Note E)
NOTES: A. Asynchronous reset signals include XF0 / 1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.
C. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the
reset vector is fetched twice, with no software wait states.
D. Control signals include STRB.
E. The R/W outputs are placed in a high-impedance state during reset and can be provided with a resistive pullup, nominally
1822 k
, if undesirable spurious writes are caused when these outputs go low.
Figure 23. Timing for RESET
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