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參數(shù)資料
| 型號： | SM320C50HFGM66 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 66 MHz, OTHER DSP, CQFP132 |
| 封裝： | TIE BAR, CERAMIC, QFP-132 |
| 文件頁數(shù)： | 6/35頁 |
| 文件大?。?/td> | 536K |
| 代理商： | SM320C50HFGM66 |
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external divide-by-one clock option
An external frequency source can be used by injecting the frequency directly into CLKIN2 with X1 left
unconnected and X2 connected to VDD. This external frequency is divided by one to generate the internal
machine cycle. The divide-by-one option is used when CLKMD1 is strapped high and CLKMD2 is strapped low.
The external frequency injected must conform to specifications listed in the timing requirements table (see
Figure 6 for more details).
switching characteristics over recommended operating conditions [H = 0.5 tc(CO)]
PARAMETER
’320C50-50
’320C50-66
UNIT
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
tc(CO)
Cycle time, CLKOUT1
40
tc(CI)
75
30
tc(CI)
75
ns
td(C2H-COH) Delay time, CLKIN2 high to CLKOUT1 high
2
9
16
2
9
16
ns
tf(CO)
Fall time, CLKOUT1
5
ns
tr(CO)
Rise time, CLKOUT1
5
ns
tw(COL)
Pulse duration, CLKOUT1 low
H – 3
H
H + 2
H – 3
H
H + 2
ns
tw(COH)
Pulse duration, CLKOUT1 high
H – 3
H
H + 2
H – 3
H
H + 2
ns
td(TP)
Delay time, transitory phase – PLL
synchronized after CLKIN2 supplied
1000 tc(C2)§
ns
Values assured by design and not tested
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’320C50-50
’320C50-66
UNIT
MIN
MAX
MIN
MAX
UNIT
tc(C2)
Cycle time, CLKIN2
40
75
30
75
ns
tf(C2)
Fall time, CLKIN2§
5
ns
tr(C2)
Rise time, CLKIN2§
5
ns
tw(C2L)
Pulse duration, CLKIN2 low
11
tc(C2) –11
9
tc(C2) –9
ns
tw(C2H)
Pulse duration, CLKIN2 high
11
tc(C2) –11
9
tc(C2) –9
ns
Clocks can be stopped only while the device executes IDLE2 when using the external divide-by-one clock option. Note that tp (the transitory
phase) occurs when restarting clock from IDLE2 in this mode.
§ Values derived from characterization data and not tested.
tr(C2)
tw(C2L)
tw(C2H)
td(TP)
tc(CO)
tc(C2)
tw(COH)
tf(CO)
tr(CO)
tf(C2)
CLKIN2
CLKOUT1
td(C2H-COH)
tw(COL)
Unstable
Figure 6. External Divide-by-One Clock Timing
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