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參數(shù)資料
| 型號： | SM320C50HFGM66 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 66 MHz, OTHER DSP, CQFP132 |
| 封裝： | TIE BAR, CERAMIC, QFP-132 |
| 文件頁數(shù)： | 20/35頁 |
| 文件大?。?/td> | 536K |
| 代理商： | SM320C50HFGM66 |
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
27
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SERIAL-PORT TRANSMIT TIMING IN TDM MODE
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]
PARAMETER
MIN
MAX
UNIT
th(TCH-TDV)
Hold time, TDAT/TADD valid after TCLK rising
0
ns
td(TCH-TFV)
Delay time, TFRM valid after TCLK rising
H
3H+10
ns
td(TC-TDV)
Delay time, TCLK to valid TDAT/TADD
20
ns
TFRM timing and waveforms shown in Figure 18 are for internal TFRM. TFRM can also be configured as external, and the TFRM external case
is illustrated in the receive timing diagram in Figure 17.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [(H = 0.5tc(CO)]
MIN
TYP
MAX
UNIT
tc(SCK)
Cycle time, serial-port clock
5.2H
8H
§
ns
tf(SCK)
Fall time, serial-port clock
8
ns
tr(SCK)
Rise time, serial-port clock
8
ns
tw(SCK)
Pulse duration, serial-port clock low/high
2.1H
ns
When SCK is generated internally.
§ The serial-port design is fully static and therefore can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency of
0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and are not tested.
A7
B2
B8
B7
A3
B12
A2
A0
A1
B0
B1
B13
B14
B0
tw(SCK)
td(TC-TDV)
th(TCH-TDV)
tr(SCK)
tf(SCK)
td(TCH-TFV)
TFRM
TADD
TDAT
TCLK
th(TCH-TDV)
B15
tc(SCK)
td(TCV-TDV)
td(TCH-TFV)
Figure 18. Serial-Port Transmit Timing in TDM Mode
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