參數(shù)資料
型號(hào)： SM320C50HFGM66
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-BIT, 66 MHz, OTHER DSP, CQFP132
封裝： TIE BAR, CERAMIC, QFP-132
文件頁(yè)數(shù)： 27/35頁(yè)
文件大?。?/td> 536K
代理商： SM320C50HFGM66
l
2K × 16-Bit On-Chip Boot ROM
l 224K × 16-Bit Maximum Addressable External Memory Space (64K Program,
64K Data, 64K I/O, and 32K Global)
l 32-Bit Arithmetic Logic Unit (ALU)
32-bit Accumulator (ACC)
32-Bit Accumulator Buffer (ACCB)
l 16-Bit Parallel Logic Unit (PLU)
l
16 × 16-Bit Multiplier, 32-Bit Product
l
11 Context-Switch Registers
l Two Buffers for Circular Addressing
l
Full-Duplex Synchronous Serial Port
l
Time-Division Multiplexed Serial Port (TDM)
l Timer With Control and Counter Registers
l
16 Software Programmable Wait-State Generators
l
Divide-by-One Clock Option
l IEEE 1149.1 Boundary Scan Logic
l
Operations Are Fully Static
l
Enhanced Performance Implanted CMOS (EPICTM) 0.72-um Technology Fabricated by
Texas Instruments
l
Packaging
141-Pin Ceramic Grid Array (GFA Suffix)
132-Lead Ceramic Quad Flat Package
(HFG Suffix)
132-Lead Plastic Quad Flat Package
(PQ Suffix)
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture
EPIC and TI are trademarks of Texas Instruments Incorporated.
The SMJ320C50 digital signal processor (DSP) is a high-performance, 16-bit, fixed-point
processor manufactured in 0.72-um double-level metal CMOS technology. The SMJ320C50 is
the first DSP from TI designed as a fully static device. Full-static CMOS design contributes to
low power consumption while maintaining high performance, making it ideal for applications
such as battery-operated communications systems, satellite systems, and advanced control
algorithms.
A number of enhancements to the basic SMJ320C2x architecture give the 'C50 a minimum 2×
performance over the previous generation. A four-deep instruction pipeline, incorporating
delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the
'C50 to perform instructions in fewer cycles. The addition of a parallel logic unit (PLU) gives
the 'C50 a method for manipulating bits in data memory without using the accumulator and
ALU. The 'C50 has additional shifting and scaling capability for proper alignment of
multiplicands or storage of values to data memory.
The 'C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes
the functional clock from the internal hardware of the 'C50, which puts it into a total-sleep
mode that uses only 7 uA. A low-logic level on an external interrupt with a duration of at least
DESCRIPTION
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