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參數(shù)資料
| 型號： | SM320C50HFGM66 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 66 MHz, OTHER DSP, CQFP132 |
| 封裝： | TIE BAR, CERAMIC, QFP-132 |
| 文件頁數(shù)： | 3/35頁 |
| 文件大?。?/td> | 536K |
| 代理商： | SM320C50HFGM66 |
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLOAD
IOL
CT
IOH
Output
Under
Test
50
Where:
IOL
=
2.0 mA (all outputs)
IOH
=
300
A (all outputs)
VLOAD =
1.5 V
CT
=
80 pF typical load circuit capacitance
Figure 1. Test Load Circuit
signal transition levels
Transistor-to-transistor logic (TTL) output levels are driven to a minimum logic-high level of 2.4 V and to a
maximum logic-low level of 0.6 V. Figure 2 shows the TTL-level outputs.
0.6 V
1 V
2 V
2.4 V
Figure 2. TTL-Level Outputs
TTL-output transition times are specified as follows:
D For a high-to-low transition, the level at which the output is said to be no longer high is 2 V, and the level
at which the output is said to be low is 1 V.
D For a low-to-high transition, the level at which the output is said to be no longer low is 1 V, and the level
at which the output is said to be high is 2 V.
Figure 3 shows the TTL-level inputs.
2.2 V
0.6 V
Figure 3. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high
is 2 V, and the level at which the input is said to be low is 0.8 V.
D For a low to high transisiton on an input signal, the level at which the input is said to be no longer low
is 0.8 V, and the level at which the input is said to be high is 2 V.
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