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參數(shù)資料
| 型號： | SM320C50HFGM66 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 66 MHz, OTHER DSP, CQFP132 |
| 封裝： | TIE BAR, CERAMIC, QFP-132 |
| 文件頁數(shù)： | 19/35頁 |
| 文件大?。?/td> | 536K |
| 代理商： | SM320C50HFGM66 |
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SERIAL-PORT RECEIVE TIMING IN TDM MODE
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5tc(CO)]
MIN
MAX
UNIT
tc(SCK)
Cycle time, serial-port clock
5.2H
ns
tf(SCK)
Fall time, serial-port clock
8
ns
tr(SCK)
Rise time, serial-port clock
8
ns
tw(SCK)
Pulse duration, serial-port clock low/high
2.1H
ns
tsu(TD-TCH)
Setup time, TDAT/TADD before TCLK rising
30
ns
th(TCH-TD)
Hold time, TDAT/TADD after TCLK rising
–3
ns
tsu(TA-TCH)
Setup time, TDAT/TADD before TCLK rising§
20
ns
th(TCH-TA)
Hold time, TDAT/TADD after TCLK rising§
– 3
ns
tsu(TF-TCH)
Setup time, TRFM before TCLK rising edge
10
ns
th(TCH-TF)
Hold time, TRFM after TCLK rising edge
10
ns
The serial-port design is fully static and therefore can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency of
0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and are not tested.
§ These parameters apply only to the first bits in the serial bit string.
TFRM timing and waveforms shown in Figure 17 are for external TFRM. TFRM also can be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 18.
A7
B2
B8
B7
A3
B12
A2
A0
A1
B0
B1
B13
B14
B15
B0
tw(SCK)
tsu(TD-TCH)
th(TCH-TD)
tsu(TA-TCH)
th(TCH-TA)
tr(SCK)
tf(SCK)
tc(SCK)
TFRM
TADD
TDAT
TCLK
th(TCH-TF)
tsu(TF -TCH)
th(TCH-TA)
Figure 17. Serial-Port Receive Timing in TDM Mode
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