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參數(shù)資料
| 型號： | SLA24C64-S |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | PROM |
| 英文描述： | 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | PLASTIC, DSO-8 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 367K |
| 代理商： | SLA24C64-S |
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SLx 24C64
Semiconductor Group
17
1999-02-02
6
Read Operations
Reading of the EEPROM data is initiated by the Master with the command byte CSR.
6.1
Random Read
Random read operations allow the master to access any memory location.
Figure 11
Random Read
Address Setting
The master generates a START condition followed by the
command byte CSW. The receipt of the CSW-byte is
acknowledged by the EEPROM with a low state on the SDA
line. Now the master transmits the EEPROM address (AHI/
ALO) to the EEPROM and the internal address counter is
loaded with the desired address.
Transmission of CSR
After the acknowledge for the EEPROM address is received,
the master generates a START condition, which terminates
the initiated write operation. Then the master transmits the
command byte CSR for read, which is acknowledged by the
EEPROM.
Transmission of
EEPROM Data
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter by one
byte.
STOP Condition from
Master
During the following clock cycle the masters releases the bus
and then transmits the STOP condition.
Command Byte
CSW
S
P
A
C
K
C
K
A
S
T
A
R
T
P
O
S
EEPROM Address
AHI
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02520
C
K
A
Data Byte
1
0
S
T
R
A
T
S
CSR
Command Byte
ALO
EEPROM Address
C
K
A
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