參數(shù)資料
型號(hào)： SLA24C64-S
廠商： INFINEON TECHNOLOGIES AG
元件分類(lèi)： PROM
英文描述： 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝： PLASTIC, DSO-8
文件頁(yè)數(shù)： 15/28頁(yè)
文件大小： 367K
代理商： SLA24C64-S
SLx 24C64
Semiconductor Group
22
1999-02-02
7.2
Protection Bit Write and Erase
For writing or erasing a protection bit the data of the respective page have to be known
by the master. The master has to present the page data as a reference for comparison
by the EEPROM. A successful comparison is necessary in order to change the value of
the protection bit.
The data of the page are not affected by the write or erase procedure of the protection
bit. The I
2C-Bus protocol is shown in figure 15 for protection bit write and figure 16 for
protection bit erase.
Figure 15
Sequence for Protection Bit Write
Figure 16
Sequence for Protection Bit Erase
The first command byte CSW followed by the address bytes AHI/ALO determines the
page to be protected. The second command byte CSW (identical content of first CSW)
is followed by the control byte CTW = 01
H for protection bit write or CTE = 03H for
protection bit erase. Depending on CTx, the addressed protection bit will be either
written or erased.
The control byte CTx is followed by 32 parameter bytes identical to the 32 data bytes of
the page to be protected or unprotected. The data of the first entered byte must be
identical to the data byte stored at the lowest address of the current page. The other
T
P
O
S
Activity
Master
SDA Line
Bus Activity
EEPROM
IED02522
P
R
T
A
T
S
Command
Byte
CSW
EEPROM
Address
ALO
Byte n
Data
Byte n+1
Data
Byte n+31
Data
1
0
00
...
C
K
A
Command
Byte
CSW
Control
Byte
CTW
EEPROM
Address
AHI
T
A
T
R
S
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
Bus
0
T
P
O
S
IED02523
P
R
T
A
T
S
1
0
00
T
A
T
R
S
Bus Activity
SDA Line
EEPROM
Activity
Master
Bus
Byte n+31
Byte n
Byte n+1
Command
Data
Control
Data
Byte
CSW
Byte
CTE
Address
EEPROM
Command
CSW
Byte
AHI
Address
EEPROM
ALO
C
K
A
C
K
A
C
K
AA
C
K
A
K
C
A
K
C
A
K
C
A
K
C
0
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