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參數(shù)資料
| 型號： | SLA24C64-S |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | PROM |
| 英文描述： | 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | PLASTIC, DSO-8 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 367K |
| 代理商： | SLA24C64-S |
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SLx 24C64
Semiconductor Group
21
1999-02-02
7.1
Protection Bit Handling
The bits of the protection memory can be addressed directly for reading or programming.
A protection bit address corresponds to the lowest address within the respective page
(A5 to A12, A0 to A4 = zero). The status of each protection bit is sensed internally. A
written state (“0”) prevents programming in the associated page. If an already protected
memory page is accidentally addressed for programming, the programming procedure
is suppressed.
The conventional I
2C-Bus protocol allows data bytes to be read and programmed only.
Therefore an independent instruction sequence for addressing and manipulation of
protection bits is implemented. For protection bit instructions the command byte CSW
with its preceding START condition followed by the associated address bytes have to be
address bytes AHI/ALO with the bit/page address A0 through A4 always at zero. The
second CSW is required for entering a control byte CTx for protection bit manipulation.
The three control bytes for read, write or erase of a protection bit are listed below
(table 3):
Table 3
Control Byte for Protection Bit Manipulation
Address
Name
Definition
Function
b7
b6
b5
b4
b3
b2
b1
b0
CTR
x
0
Protection bit read
CTW
x
0
1
Protection bit write
CTE
x
1
Protection bit erase
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| SLA24C64-S/P | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
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