參數(shù)資料
型號(hào)： TSB41BA3-EP
英文描述： IC APEX 20KE FPGA 400K 672-FBGA
中文描述： 軍事增強(qiáng)塑料的IEEE 1394b三端口電纜收發(fā)器/仲裁器
文件頁(yè)數(shù)： 13/50頁(yè)
文件大?。?/td> 662K
代理商： TSB41BA3-EP
SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)
(continued)
device
PARAMETER
TEST CONDITION
See Note 2
MIN
TYP
115
MAX
UNIT
IDD
Supply current
See Note 3
97
mA
See Note 4
75
IDD(ULP)
Supply current
—
ultralow power mode
VDD = 3.3 V,
Ports disabled, PD = 0 V,
LPS = 0 V
400-k
resistor
VDD = 2.7 V,
VDD = 3 V to 3.6 V, IOH =
–
4 mA
TA = 25
°
C,
150
μ
A
V(TH)
Power status threshold, CPS input
4.7
7.5
V
VOH
High-level output voltage, CTL0, CTL1,
High level out ut voltage, CTL0, CTL1,
D0
–
D7, CNA, C/LKON, SYSCLK outputs
IOH =
–
4 mA
2.2
V
2.8
V
VOL
Low-level output voltage, CTL0, CTL1,
D0
–
D7, CNA, C/LKON, SYSCLK outputs
IOL = 4 mA
0.4
V
VOH(AJ)
High-level Annex J output voltage, CTL0,
CTL1, D0
–
D7, C/LKON, SYSCLK outputs
Annex J: IOH =
–
9 mA,
ISO = 0 V,
VDD
≥
3 V
Annex J: IOL = 9 mA,
ISO = 0 V,
VDD
≥
3 V
ISO = 3.6 V,
VI = 0 V to VDD,VDD_5V = VDD
ISO = 3.6 V,
VI = 0 V to VDD,VDD_5V = VDD
VDD_5V = VDD
VDD
–
0.4
V
VOL(AJ)
Low-level Annex J output voltage, CTL0,
CTL1, D0
–
D7, C/LKON, SYSCLK outputs
VDD_5V = VDD
0.4
V
I(BH+)
Positive peak bus holder current, D0
–
D7,
CTL0
–
CTL1, LREQ
VDD = 3.6 V,
0.05
1
mA
I(BH
–
)
Negative peak bus holder current, D0
–
D7,
CTL0
–
CTL1, LREQ
VDD = 3.6 V,
–
1.0
–
0.05
mA
II
Input current, LREQ, LPS, PD, TESTM,
SM, SE, PC0
–
PC2 inputs
ISO = 0 V, VDD = 3.6 V
1
μ
A
IOZ
Off-state output current, CTL0, CTL1,
D0
–
D7, C/LKON I/O
’
s
VO = VDD or 0 V
±
5
μ
A
I(IRST)
Pullup current, RESET input
VI = 1.5 V or 0 V
VDD_5V = VDD, ISO = 0 V
VDD
≥
3 V
VDD_5V = VDD, ISO = 0 V,
Vref = VDD
×
0.4, VDD
≥
3 V
ISO = 0 V,
VDD
≥
3 V
ISO = 0 V,
Vref = VDD
×
0.4, VDD
≥
3 V
At rated IO current
–
90
–
20
μ
A
VIT+
Positive input threshold voltage, LREQ,
CTL0, CTL1, D0
–
D7 inputs
VDD/2+0.3
VDD/2+0.9
V
Positive input threshold voltage, LPS inputs
Vref+1
VIT
–
Negative input threshold voltage, LREQ,
CTL0, CTL1, D0
–
D7 inputs
VDD_5V = VDD
VDD/2
–
0.9
VDD/2
–
0.3
V
Negative input threshold voltage, LPS
inputs
VDD_5V = VDD,
Vref+0.2
VO
Measured at cable power side of resistor.
This parameter applicable only when ISO is low.
NOTES:
2. Transmit max packet (three ports transmitting max size isochronous packet
—
4096 bytes, sent on every isochronous interval, s400,
data value of 0xCCCCCCCCh), VDD = 3.3 V, TA = 25
°
C
3. Repeat typical packet (one port receiving DV packets on every isochronous interval, two ports repeating the packet, s100), VDD
=
3.3 V, TA = 25
°
C
4. Idle (three ports transmitting cycle starts), VDD = 3.3 V, TA = 25
°
C
TPBIAS output voltage
1.665
2.015
V
相關(guān)PDF資料
PDF描述
TSB41LV03PFP IC APEX 20KE FPGA 600K 652-BGA
TSB41AB2I IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER
TSB41LV03AI IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER
TSC692E 672-pin FineLine BGA
TSC695F IC,FPGA,57120-CELL,CMOS,BGA,1020PIN,PLASTIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB41BA3IPFP 制造商:Rochester Electronics LLC 功能描述:1394B-2002 3-PORT PHYSICAL LAYER DEVICE - Bulk 制造商:Texas Instruments 功能描述:CBL TRNSCVR 6TR 6TX 6RX 80HTQFP - Trays
TSB41BA3PFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:CBL TRNSCVR 6TR 6TX 6RX 80HTQFP - Trays
TSB41LV01 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER
TSB41LV01PAP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TSB41LV02 WAF 制造商:Texas Instruments 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*