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參數(shù)資料
| 型號(hào)： | SI5317D-C-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 7/46頁 |
| 文件大小： | 0K |
| 描述： | IC CLK JITTER CLEANR PROG 36QFN |
| 應(yīng)用說明： | SI5315/17 Crystal Selection AppNote |
| 特色產(chǎn)品： | Si5317 Jitter Cleaning Clock |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | DSPLL® |
| 類型： | 抖動(dòng)消除器 |
| PLL： | 帶旁路 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 100MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 36-QFN（6x6） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 628 (CN2011-ZH PDF) |
| 其它名稱： | 336-1920 |
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Si5317
Rev. 1.1
15
3. Frequency Plan Tables
For ease of use, the Si5317 is pin-controlled to enable simple device configuration of the frequency range plan and
PLL loop bandwidth via a predefined look-up table. The DSPLL has been optimized for jitter performance and
tunability for each frequency range and PLL loop bandwidth provided in Table 9 on page 22.
Many of the control inputs are three levels: High, Low, and Medium. High and Low are standard voltage levels
determined by the supply pins: VDD and Ground. If the input pin is left floating, it is driven to nominally half of VDD.
Effectively, this creates three logic levels for these controls. See section 6. "Power Supply Filtering" on page 33 and
section 1.2. "Three-Level Input Pins (Example with External Resistors)" on page 9 for additional information.
3.1. Frequency Range Plan
The input to output clock frequency range is set by the 3-level FRQSEL[3:0] and FRQTBL pins. The CKIN and
CKOUT is the same frequency range as specified in Table 8. Due to the wide tunability of the Si5317, each
frequency plan provides overlap between adjacent settings. To select a frequency plan, the desired frequency
should be selected as close to the defined center frequency. In certain cases where the desired frequency is
exactly between two overlapping plans, either FRQTBL and FRQSEL setting can be used.
3.1.1. PLL Loop Bandwidth Plan
The Si5317's loop bandwidth ranges from 60 Hz to 8.4 kHz. For each frequency range, the corresponding loop
bandwidth is provided in a simple look-up table (see Table 9 on page 22). The loop bandwidth is digitally
programmable using the three-level BWSEL [1:0] input pins.
3.2. Output Skew Adjustment
The overall device skew (CKIN to CKOUTn phase delay) is adjustable via the INC and DEC input pins. A positive
edge triggered pulse applied to the INC pin increases the device skew defined by Table 8, INC/DEC step size, for
each given frequency plan. The identical operation on the DEC pin decreases the skew by the same amount.
Using the INC and DEC pins, there is no limit to the range of skew adjustment that can be made. Following a
powerup or reset, the overall device skew will revert to the reset value, although the input-to-output skew is
effectively random. The rate of change for each INC/DEC operation is defined by the selected loop bandwidth,
BWSEL[1:0].
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5317D-C-GMR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| Si5317-EVB | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Si5317 Eval Board RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5318 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| SI5318-EVB | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 SI5318 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5318-F-BC | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 SONET/SDH PRECISION CLOCK MULT.IC 19/155 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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