參數(shù)資料
型號(hào)： SI5317D-C-GM
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 6/46頁(yè)
文件大?。?/td> 0K
描述： IC CLK JITTER CLEANR PROG 36QFN
應(yīng)用說明： SI5315/17 Crystal Selection AppNote
特色產(chǎn)品： Si5317 Jitter Cleaning Clock
標(biāo)準(zhǔn)包裝： 490
系列： DSPLL®
類型： 抖動(dòng)消除器
PLL： 帶旁路
輸入： 時(shí)鐘，晶體
輸出： CML，CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 100MHz
除法器/乘法器： 無/無
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 36-QFN（6x6）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 628 (CN2011-ZH PDF)
其它名稱： 336-1920
Si5317
14
Rev. 1.1
2. Functional Description
Figure 5. Detailed Block Diagram
2.1. Overview
The Si5317 is a 1:1 jitter-attenuating precision clock for applications requiring sub 1 ps jitter performance. The
Si5317 accepts one clock input ranging from 1 to 711 MHz and generates two clock outputs at the same frequency
ranging from 1 to 711 MHz. The Si5317 is based on Silicon Laboratories' 3rd-generation DSPLL technology,
which provides jitter attenuation on any frequency in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The nominal operating frequency is selectable from a look-up table.
The Si5317 PLL loop bandwidth (BW) is selectable via the BWSEL[1:0] pins and supports a range from 60 Hz to
8.4 kHz.
The Si5317 monitors the input clock for loss-of-signal (LOS) and provides a LOS alarm when it detects missing
pulses on the input clock. The device monitors the lock status of the DSPLL. The lock detect algorithm works by
continuously monitoring the phase of the input clock in relation to the phase of the feedback clock.
The Si5317 provides a VCO freeze capability that allows the device to continue generation of a stable output clock
when the selected input clock is lost. During VCO freeze, the DSPLL latches its VCO settings and uses its XA/XB
clock as its frequency reference.
The Si5317 has two output clock drivers and can be configured as four single-ended or two differential outputs.
The signal format of the clock output is selectable to support LVPECL, LVDS, CML, or CMOS loads. The device
operates from a single 1.8, 2.5, or 3.3 V supply. The use of LVPECL requires a VDD > 2.25 V.
DSPLL
LOS
LOL
BWSEL[1:0]
CKIN+
CKIN–
CKOUT+
CKOUT–
VDD (1.8, 2.5, or 3.3 V)
GND
2
FRQSEL[3:0]
RST
RATE[1:0]
XA
XB
fOSC
2
f3
Frequency
Control
Bandwidth
Control
Alarms
Control
External Crystal or
Reference Clock
FRQTBL
Voltage
Regulator with
High PSRR
SFOUT[1:0]
2
CKOUT+
CKOUT–
Skew Control
INC
DEC
DBL2_BY
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5317D-C-GMR 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
Si5317-EVB 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Si5317 Eval Board RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
SI5318 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SONET/SDH PRECISION CLOCK MULTIPLIER IC
SI5318-EVB 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 SI5318 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
SI5318-F-BC 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 SONET/SDH PRECISION CLOCK MULT.IC 19/155 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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