參數(shù)資料
型號(hào): SI5317D-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 38/46頁
文件大?。?/td> 0K
描述: IC CLK JITTER CLEANR PROG 36QFN
應(yīng)用說明: SI5315/17 Crystal Selection AppNote
特色產(chǎn)品: Si5317 Jitter Cleaning Clock
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類型: 抖動(dòng)消除器
PLL: 帶旁路
輸入: 時(shí)鐘,晶體
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 100MHz
除法器/乘法器: 無/無
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
產(chǎn)品目錄頁面: 628 (CN2011-ZH PDF)
其它名稱: 336-1920
Si5317
Rev. 1.1
43
Table 17. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
0.50 BSC.
E5.42 REF.
D5.42 REF.
E2
4.00
4.20
D2
4.00
4.20
GE
4.53
GD
4.53
X
0.28
Y0.89 REF.
ZE
6.31
ZD
6.31
Notes (General):
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3.
This Land Pattern Design is based on IPC-SM-782 guidelines.
4.
All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1.
All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 m minimum, all the way around the pad.
Notes (Stencil Design):
1.
A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2.
The stencil thickness should be 0.125 mm (5 mils).
3.
The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4.
A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Notes (Card Assembly):
1.
A No-Clean, Type-3 solder paste is recommended.
2.
The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
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