參數(shù)資料
型號: SI5317D-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 31/46頁
文件大?。?/td> 0K
描述: IC CLK JITTER CLEANR PROG 36QFN
應(yīng)用說明: SI5315/17 Crystal Selection AppNote
特色產(chǎn)品: Si5317 Jitter Cleaning Clock
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類型: 抖動(dòng)消除器
PLL: 帶旁路
輸入: 時(shí)鐘,晶體
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 100MHz
除法器/乘法器: 無/無
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
產(chǎn)品目錄頁面: 628 (CN2011-ZH PDF)
其它名稱: 336-1920
Si5317
Rev. 1.1
37
7
6
XB
XA
I
Analog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use
internal oscillator-based reference. Crystal or reference clock
selection is set by the XTAL/CLOCK pin. See “AN591:
Crystal Selection for the Si5315 and Si5317.”
8,31
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
11
15
RATE0
RATE1
I
3-Level
External Crystal or Reference Clock Rate.
Note:
See Table 13 for settings.
14
DBL2_BY
I
3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Bypass mode is not supported for CMOS clock outputs.
16
17
CKIN+
CKIN–
IMulti
Clock Input.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from Table 9
18
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indica-
tor.
0 = PLL locked
1 = PLL unlocked
19
DEC
I
LVCMOS
Skew Decrement.
This edge-triggered pin decreases the input to output device
skew. There is no limit on the range of skew adjustment by
this method. Detailed operations and timing characteristics
for this pin are found in Section 3.2, Table 8.
This pin has a weak pull-down.
20
INC
I
LVCMOS
Skew Increment.
This edge-triggered pin increases the input to output device
skew. There is no limit on the range of skew adjustment by
this method. Detailed operations and timing characteristics
for this pin are found in Section 3.2, Table 8.
This pin has a weak pull-down.
Table 14. Si5317 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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