
Si5317
Rev. 1.1
7
LVCMOS Output Pins
Output Voltage Low
VOL
IO =2mA
VDD =1.62V
——
0.4
V
IO =2mA
VDD =2.97V
——
0.4
V
Output Voltage High
VOH
IO =–2mA
VDD =1.62V
VDD –0.4
—
V
IO =–2mA
VDD =2.97V
VDD –0.4
—
V
Single-Ended Reference Clock Input Pin XA (XB with cap to gnd)
Input Resistance
XARIN
XTAL/RefCLK
RATE[1:0] = LM, ML, MH, or
HM
—12
—
k
Input Voltage Level Limits
XAVIN
0—
1.2
V
Input Voltage Swing
XAVPP
0.5
—
1.2
VPP
Differential Reference Clock Input Pins (XA/XB)
Input Resistance
XA/XBRIN
XTAL/RefCLK
RATE[1:0] = LM, ML, MH, or
HM
—12
—
k
Differential Input Voltage
Level Limits
XA/XBVIN
0—
1.2
V
Input Voltage Swing
XAVPP/XBVPP
0.5
—
2.4
VPP
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. LVPECL outputs require VDD > 2.25 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
3. No overshoot or undershoot.