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參數(shù)資料
| 型號： | SDA9188-3X |
| 廠商： | SIEMENS A G |
| 元件分類： | 畫面疊加 |
| 英文描述： | Picture-in-Picture Processor with On-Chip PLL |
| 中文描述： | PICTURE-IN-PICTURE IC, PDSO28 |
| 文件頁數(shù)： | 6/31頁 |
| 文件大小： | 462K |
| 代理商： | SDA9188-3X |
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Semiconductor Group
6
Circuit Description
Data Transfer
The digital data are transferred under the control of LL3I, BLNI and VSI on pins YS0-YS5 and
UVS0-UVS3. The decimated data are stored automatically. Either R, G, B, or Y, -U, -V analog
signals are available at the outputs OUT1-OUT3. The validity of the signals is identified by
SELECT = 1. In a digital system environment the input is controlled by LL3P, HSP and VSP.
Inset Data Reduction
The data rate at the inputs YS0-YS5, UVS0-UVS3 is 13.5 MHz in multiplexed format,
see figure 1
.
In order to reduce the quantity of data which have to be stored and to prevent artifacts in the inset
picture, nine pixels are processed into one inset pixel for a 1/9 picture. For the 1/16 picture 16 pixels
are processed into one inset pixel.
This is done by horizontal and vertical averaging of pixels:
The characteristic of decimation for the luminance signal is 1-1-1 for 1/9- and 1-1-1-1 for 1/16
picture. Crominance signal: 1-2-1 for 1/9 and 1-1-1-1 for 1/16 picture.
Figure 1
Input Data Format
SDA 9188-3X
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