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參數(shù)資料
| 型號： | SDA9188-3X |
| 廠商： | SIEMENS A G |
| 元件分類： | 畫面疊加 |
| 英文描述： | Picture-in-Picture Processor with On-Chip PLL |
| 中文描述： | PICTURE-IN-PICTURE IC, PDSO28 |
| 文件頁數(shù)： | 18/31頁 |
| 文件大小： | 462K |
| 代理商： | SDA9188-3X |
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Semiconductor Group
18
SDA 9188-3X
Register 7
(Address 07
H
)
Register 8
(Address 08
H
)
Bit
Function
Name
Remarks
d4:d0
d5
d6
d7
Delay of the VSP pulse
0 = Vertical noise reduction OFF
1 = Vertical noise reduction ON
0 = Check for correct TV standard inactive
1 = Check for correct TV standard active
0 = PAL/NTSC
1 = SECAM
VSPDEL
VSPIS
STATP
AMSEC
Setting is possible in steps
of 2,37
μ
s (50 Hz or
1,185
μ
s 100 Hz)
(see measuring circuit 6)
Noise reduction for the
vertical pulse of the parent
channel (should be set to
‘1’ under normal
conditions).
If the check for the correct
TV standard is active a full
frame display is only
possible if the number of
lines is exactly according
the TV standard:
312.5 (50 Hz)
262.5 (60 Hz)
Doubling of the gain if a
sufficient SECAM decoder
without delay line is used
Bit
Function
Name
Remarks
d3:d0
d4
d7:d5
0000 = min. brightness of the border frame
1111 = max. brightness of the border frame
0 = brightness of the border frame can be
selected by FRY
1 = brightness of the border frame can be
selected by FRY5:2
not used to be set to “0“.
FRY5:2
FRYEN
Setting only valid if the bit
d4 is set to ‘1’
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