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參數(shù)資料
| 型號： | SDA9188-3X |
| 廠商： | SIEMENS A G |
| 元件分類： | 畫面疊加 |
| 英文描述： | Picture-in-Picture Processor with On-Chip PLL |
| 中文描述： | PICTURE-IN-PICTURE IC, PDSO28 |
| 文件頁數(shù)： | 17/31頁 |
| 文件大?。?/td> | 462K |
| 代理商： | SDA9188-3X |
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Semiconductor Group
17
SDA 9188-3X
Register 6
(Address 06
H
)
Bit
Function
Name
Remarks
d4:d0
d5
d6
d7
Setting the delay of VSI
(see test circuit 6)
0 = Vertical noise reduction inactive
1 = Vertical noise reduction active
0 = Check for correct TV standard inactive
1 = Check for correct TV standard active
0 = Field display
1 = Frame display
VSIDEL
VSIS
STATI
FRAME
Setting is possible in steps
of 2,37
μ
s (see
measurement circuit 6)
Noise reduction of the VSI
pulse (should be set to ‘1’
under normal conditions.)
If the check is active a full
frame display is only
possible if the number of
lines is exactly according
the TV standard:
312.5 (50 Hz)
262.5 (60 Hz)
Only active if the line
number and the interlace
mode are equal for both
inset and parent signal.
If the display mode is 100/
120 Hz or progressive
scan d7 has to be set to 0
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