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參數(shù)資料
| 型號(hào)： | SDA9188-3X |
| 廠商： | SIEMENS A G |
| 元件分類： | 畫面疊加 |
| 英文描述： | Picture-in-Picture Processor with On-Chip PLL |
| 中文描述： | PICTURE-IN-PICTURE IC, PDSO28 |
| 文件頁數(shù)： | 1/31頁 |
| 文件大?。?/td> | 462K |
| 代理商： | SDA9188-3X |
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Features
G
On-chip PLL
G
Full frame display for 50/60 Hz in order to increase the
vertical resolution and to suppress moving artifacts.
G
Compatibility to the 16:9 display format by means of
independent setting of the vertical and horizontal
decimation factors and the width of the border frame
G
Decimation of the Y, U, V data for pictures sizes 1/9
and 1/16 with 6 bits width of the input word without
rounding error
G
Intermediate storage of the inset picture (on-chip-memory)
G
RGB- or Y-, U-, V-signal generation
G
100% pin- and software compatible with SDA 9188X if external PLL is used
G
Increased bandwith of analog outputs due to higher output currents
G
New select function for multi-PIP feature
Functional Description
The SDA 9188-3X Picture-in-Picture (PIP) processor with on-chip PLL combines two asynchronous
picture sources so that a small moving picture (the inset picture) can be superimposed in a moving
picture of normal size (the parent picture).
The components of the video signal of the inset source have to be fed in a digitized form to the
SDA 9188-3X (
figure 1
). Amplitude resolution of the signal components is 6 bit at a sampling rate
of 13.5 MHz for the luminance signal and 3.375 MHz for the chrominance signals.
Type
Ordering Code
Package
SDA 9188-3X
Q67100-H5142
P-DSO-28-3 (350 mil) (SMD)
Picture-in-Picture Processor with On-Chip PLL
Preliminary Data
MOS IC
SDA 9188-3X
Semiconductor Group
1
08.93
P-DSO-28-3
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