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參數(shù)資料
| 型號(hào)： | SCANPSC110 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| 中文描述： | 掃描橋?qū)哟魏投帱c(diǎn)尋址JTAG端口（IEEE1149.1系統(tǒng)測(cè)試支援） |
| 文件頁數(shù)： | 4/29頁 |
| 文件大?。?/td> | 459K |
| 代理商： | SCANPSC110 |
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Table of Contents
(Continued)
TABLE 2. Detailed Pin Description Table
(Continued)
Pin
#
(SOIC
& LCC)
14, 21
Name
I/O
(Note 1)
Description
GND
Ground potential
Power supply pins 0V.
Note 1:
All pins are active HIGH unless otherwise noted.
Overview of SCANPSC110F Bridge Functions
SCANPSC110F BRIDGE ARCHITECTURE
Figure 1 shows the basic architecture of the ’PSC110F. The
device’s major functional blocks are illustrated here. The
TAP Controller, a 16-state state machine, is the central con-
trol for the device. The instruction register and various test
data registers can be scanned to exercise the various func-
tions of the ’PSC110F (these registers behave as defined in
IEEE Std. 1149.1).
The ’PSC110F selection controller provides the functionality
that allows the 1149.1 protocol to be used in a multi-drop en-
vironment. It primarily compares the address input to the slot
identification and enables the ’PSC110F for subsequent
scan operations.
The Local Scan Port Network (LSPN) contains multiplexing
logic used to select different port configurations. The LSPN
control block contains the Local Scan Port Controllers
(LSPC) for each Local Scan Port (LSP
, LSP
, and LSP
).
This control block receives input from the ’PSC110F instruc-
tion register, mode register, and the TAP controller. Each lo-
cal port contains all four (4) boundary scan signals needed to
interface with the local TAPs.
SCANPSC110F BRIDGE STATE MACHINES
The ’PSC110F is IEEE 1149.1-compatible, in that it supports
all required 1149.1 operations. In addition, it supports a
higher level of protocol, (Level 1), that extends the IEEE
1149.1 Std. to a multi-drop environment.
DS100327-3
FIGURE 1. SCANPSC110F Bridge Architecture
S
www.national.com
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