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參數(shù)資料
| 型號(hào)： | SCANPSC110 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| 中文描述： | 掃描橋?qū)哟魏投帱c(diǎn)尋址JTAG端口（IEEE1149.1系統(tǒng)測(cè)試支援） |
| 文件頁數(shù)： | 12/29頁 |
| 文件大?。?/td> | 459K |
| 代理商： | SCANPSC110 |
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Level 2 Protocol
(Continued)
1.
Instructions that insert a ’PSC110F register into the ac-
tive scan chain so that the register can be captured or
updated (BYPASS, SAMPLE/PRELOAD, EXTEST, ID-
CODE, MODESEL, MCGRSEL, LFSRSEL, CNTRSEL).
Instructions that configure local ports or control the op-
eration of the linear feedback shift register and counter
registers
(UNPARK,
PARKTRL,
PAUSE, GOTOWAIT, SOFTRESET, LFSRON, LFS-
ROFF CNTRON, CNTROFF). These instructions, along
with any other yet undefined Op-Codes, will cause the
device identification register to be inserted into the ac-
tive scan chain.
2.
PARKRTI,
PARK-
LEVEL 2 INSTRUCTION DESCRIPTIONS
BYPASS:
The BYPASSinstruction selects the bypass regis-
ter for insertion into the active scan chain when the
’PSC110F is selected.
EXTEST:
boundary-scan register for insertion into the active scan
chain. The boundary-scan register consists of seven
“sample only” shift cells connected to the S
and OE in-
puts. On the ’PSC110F, the EXTESTinstruction performs the
same function as the SAMPLE/PRELOAD instruction, since
there aren’t any scannable outputs on the device.
SAMPLE/PRELOAD:
The SAMPLE/PRELOAD instruction
selects the boundary-scan register for insertion into the ac-
tive scan chain. The boundary-scan register consists of
seven “sample only” shift cells connected to the S
(0–5)
and
OE inputs.
IDCODE:
The IDCODE instruction selects the device identi-
fication register for insertion into the active scan chain. When
IDCODE is the current active instruction the device identifi-
cation “0FC0E01F” Hex is captured upon exiting the
Capture-DR state.
The
EXTEST
instruction
selects
the
TABLE 5. Level 2 Protocol and Op-Codes
Instructions
Hex Op-Code
FF
00
81
AA
E7
C5
84
C6
C3
8E
03
88
C9
0C
8D
CE
0F
90
TBD
Binary Op-Code
11111111
00000000
10000001
10101010
11100111
11000101
10000100
11000110
11000011
10001110
00000011
10001000
11001001
00001100
10001101
11001110
00001111
10010000
TBD
Data Register
BYPASS
EXTEST
SAMPLE/PRELOAD
IDCODE
UNPARK
PARKTLR
PARKRTI
PARKPAUSE
GOTOWAIT
*
MODESEL
MCGRSEL
SOFTRESET
LFSRSEL
LFSRON
LFSROFF
CNTRSEL
CNTRON
CNTROFF
Other Undefined
Bypass Register
Boundary-Scan Register
Boundary-Scan Register
Device Identification Register
Device Identification Register
Device Identification Register
Device Identification Register
Device Identification Register
Device Identification Register
Mode Register
Multi-Cast Group Register
Device Identification Register
Linear Feedback Shift Register
Device Identification Register
Device Identification Register
32-Bit TCK Counter Register
Device Identification Register
Device Identification Register
Device Identification Register
Note 4:
All other instructions act on selected ’PSC110Fs only.
UNPARK:
This instruction unparks the Local Scan Port Net-
work and inserts it into the active scan chain as configured
by the Mode register (see Table 4). Unparked LSPs are se-
quenced synchronously with the ’PSC110F’s TAP controller.
When a LSP has been parked in the Test-Logic-Reset or
Run-Test/Idle state, it will not become unparked until the
’PSC110F’s TAP Controller enters the Run-Test/Idle state
following the UNPARK instruction. If an LSP has been
parked in one of the stable pause states (Pause-DR or
Pause-IR), it will not become unparked until the ’PSC110F’s
TAP Controller enters the respective pause state. (See Fig-
ures 9, 10, 11, 12).
PARKTLR:
This instruction causes all unparked LSPs to be
parked in the Test-Logic-Reset TAP controller state and re-
moves the LSP network from the active scan chain. The LSP
controllers keep the LSPs parked in the Test-Logic-Reset
state by forcing their respective TMS
output with a constant
logic “1” while the LSP controller is in the Parked-TLR state
(see Figure 4 ).
PARKRTI:
This instruction causes all unparked LSPs to be
parked in the Run-Test/Idlestate. When a LSP
is active (un-
parked), its TMS
signals follow TMS
and the LSP
control-
ler state transitions are synchronized with the TAP Controller
state transitions of the ’PSC110F. When the instruction reg-
ister is updated with the PARKRTI instruction, TMS
will be
forced to a constant logic “0”, causing the unparked local
TAP Controllers to be parked in the Run-Test/Idle state.
When an LSP
n
is parked, it is removed from the active scan
chain.
PARKPAUSE:
The PARKPAUSE instruction has dual func-
tionality. It can be used to park unparked LSPs or to unpark
parked LSPs. The instruction places all unparked LSPs in
S
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