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| 型號： | SC16C550IB48,128 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 639K |
| 代理商： | SC16C550IB48,128 |
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Philips Semiconductors
SC16C550
UART with 16-byte FIFO and IrDA encoder/decoder
Product data
Rev. 05 — 19 June 2003
29 of 52
9397 750 11619
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C550 is connected. Four bits of
this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
0
LSR[0]
Receive data ready.
Logic 0 = No data in receive holding register or FIFO (normal default
condition).
Logic 1 = Data has been received and is saved in the receive holding
register or FIFO.
Table 19:
Line Status Register bits description…continued
Bit
Symbol
Description
Table 20:
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
Data Carrier Detect. DCD (Active-HIGH, logical 1). Normally this bit is
the complement of the DCD input. In the loop-back mode this bit is
equivalent to the OUT2 bit in the MCR register.
6
MSR[6]
Ring Indicator. RI (Active-HIGH, logical 1). Normally this bit is the
complement of the RI input. In the loop-back mode this bit is equivalent
to the OUT1 bit in the MCR register.
5
MSR[5]
Data Set Ready. DSR (Active-HIGH, logical 1). Normally this bit is the
complement of the DSR input. In loop-back mode this bit is equivalent to
the DTR bit in the MCR register.
4
MSR[4]
Clear To Send. CTS. CTS functions as hardware ow control signal
input if it is enabled via EFR[7]. The transmit holding register ow control
is enabled/disabled by MSR[4]. Flow control (when enabled) allows
starting and stopping the transmissions based on the external modem
CTS signal. A logic 1 at the CTS pin will stop SC16C550 transmissions
as soon as current character has nished transmission. Normally
MSR[4] is the complement of the CTS input. However, in the loop-back
mode, this bit is equivalent to the RTS bit in the MCR register.
3
MSR[3]
DCD [1]
Logic 0 = No DCD change (normal default condition).
Logic 1 = The DCD input to the SC16C550 has changed state since
the last time it was read. A modem Status Interrupt will be generated.
2
MSR[2]
RI [1]
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C550 has changed from a logic 0 to
a logic 1. A modem Status Interrupt will be generated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C550IN40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C550IN40,112 | 功能描述:IC UART SINGLE W/FIFO 40-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - UART（通用異步接收器/發(fā)送器） 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 特點(diǎn):* 通道數(shù):2，DUART FIFO's:16 字節(jié) 規(guī)程:RS232，RS485 電源電壓:2.25 V ~ 5.5 V 帶并行端口:- 帶自動流量控制功能:是 帶IrDA 編碼器/解碼器:是 帶故障啟動位檢測功能:是 帶調(diào)制解調(diào)器控制功能:是 帶CMOS:是 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:托盤 其它名稱:XR16L2551IM-F-ND |
| SC16C554 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C554B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
| SC16C554B_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
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