參數(shù)資料
型號: SAK-XC2237M-104F40L
廠商: Infineon Technologies
文件頁數(shù): 38/107頁
文件大?。?/td> 0K
描述: IC MCU 16BIT 320KB FLASH 64LQFP
標(biāo)準(zhǔn)包裝: 1,900
系列: XC22xxM
核心處理器: C166SV2
芯體尺寸: 16/32-位
速度: 40MHz
連通性: CAN,EBI/EMI,I²C,LIN,SPI,SSC,UART/USART,USI
外圍設(shè)備: I²S,POR,PWM,WDT
輸入/輸出數(shù): 38
程序存儲器容量: 832KB(832K x 8)
程序存儲器類型: 閃存
RAM 容量: 50K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-LQFP
包裝: 帶卷 (TR)
其它名稱: SP000720382
XC2238M, XC2237M
XC2000 Family / Base Line
Functional Description
Data Sheet
36
V2.1, 2011-07
to a dedicated vector table location). The occurrence of a hardware trap is also indicated
by a single bit in the trap flag register (TFR). Unless another higher-priority trap service
is in progress, a hardware trap will interrupt any ongoing program execution. In turn,
hardware trap services can normally not be interrupted by standard or PEC interrupts.
Depending on the package option up to 3 External Service Request (ESR) pins are
provided. The ESR unit processes their input values and allows to implement user
controlled trap functions (System Requests SR0 and SR1). In this way reset, wakeup
and power control can be efficiently realized.
Software interrupts are supported by the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number. Alternatively to emulate an interrupt by software a
program can trigger interrupt requests by writing the Interrupt Request (IR) bit of an
interrupt control register.
3.6
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system built into the XC223xM provides a broad range of
debug and emulation features. User software running on the XC223xM can be debugged
within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface. This
either consists of the 2-pin Device Access Port (DAP) or of the JTAG port conforming to
IEEE-1149. The debug interface can be completed with an optional break interface.
The debugger controls the OCDS with a set of dedicated registers accessible via the
debug interface (DAP or JTAG). In addition the OCDS system can be controlled by the
CPU, e.g. by a monitor program. An injection interface allows the execution of OCDS-
generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported, as is the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing data can be obtained via the debug interface, or via the external bus interface
for increased performance.
Tracing of program execution is supported by the XC2000 Family emulation device.
The DAP interface uses two interface signals, the JTAG interface uses four interface
signals, to communicate with external circuitry. The debug interface can be amended
with two optional break lines.
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