參數(shù)資料
型號: SAK-XC2237M-104F40L
廠商: Infineon Technologies
文件頁數(shù): 37/107頁
文件大小: 0K
描述: IC MCU 16BIT 320KB FLASH 64LQFP
標準包裝: 1,900
系列: XC22xxM
核心處理器: C166SV2
芯體尺寸: 16/32-位
速度: 40MHz
連通性: CAN,EBI/EMI,I²C,LIN,SPI,SSC,UART/USART,USI
外圍設(shè)備: I²S,POR,PWM,WDT
輸入/輸出數(shù): 38
程序存儲器容量: 832KB(832K x 8)
程序存儲器類型: 閃存
RAM 容量: 50K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-LQFP
包裝: 帶卷 (TR)
其它名稱: SP000720382
XC2238M, XC2237M
XC2000 Family / Base Line
Functional Description
Data Sheet
35
V2.1, 2011-07
3.5
Interrupt System
The architecture of the XC223xM supports several mechanisms for fast and flexible
response to service requests; these can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to be
serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
Where in a standard interrupt service the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the
current CPU activity to perform a PEC service. A PEC service implies a single byte or
word data transfer between any two memory locations with an additional increment of
either the PEC source pointer, the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source-related vector location. PEC services are
particularly well suited to supporting the transmission or reception of blocks of data. The
XC223xM has eight PEC channels, each whith fast interrupt-driven data transfer
capabilities.
With a minimum interrupt response time of 7/11
1) CPU clocks, the XC223xM can react
quickly to the occurrence of non-deterministic events.
Interrupt Nodes and Source Selection
The interrupt system provides 96 physical nodes with separate control register
containing an interrupt request flag, an interrupt enable flag and an interrupt priority bit
field. Most interrupt sources are assigned to a dedicated node. A particular subset of
interrupt sources shares a set of nodes. The source selection can be programmed using
the interrupt source selection (ISSR) registers.
External Request Unit (ERU)
A dedicated External Request Unit (ERU) is provided to route and preprocess selected
on-chip peripheral and external interrupt requests. The ERU features 4 programmable
input channels with event trigger logic (ETL) a routing matrix and 4 output gating units
(OGU). The ETL features rising edge, falling edge, or both edges event detection. The
OGU combines the detected interrupt events and provides filtering capabilities
depending on a programmable pattern match or miss.
Trap Processing
The XC223xM provides efficient mechanisms to identify and process exceptions or error
conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap
causes an immediate system reaction similar to a standard interrupt service (branching
1) Depending if the jump cache is used or not.
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