參數(shù)資料
型號： SAF-XC2735X-72F80L
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PQFP64
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-64
文件頁數(shù)： 93/101頁
文件大?。?/td> 862K
代理商： SAF-XC2735X-72F80L
XC2735X
XC2000 Family Derivatives / Base Line
Electrical Parameters
Data Sheet
91
V2.0, 2009-03
Figure 21
USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration where the slave select signal
is low-active and the serial clock signal is not shifted and not inverted.
t2
t1
USIC_SSC_TMGX.VSD
Clock Output
SCLKOUT
Data Output
DOUT
t
3
t
3
t5
Data
valid
t4
First Transmit
Edge
Data Input
DX0
Select Output
SELOx
Active
Master Mode Timing
Slave Mode Timing
t11
t10
Clock Input
DX1
Data Output
DOUT
t14
Data
valid
Data Input
DX0
Select Input
DX2
Active
t13
t12
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched
.
Receive
Edge
Last Receive
Edge
Inactive
Transmit
Edge
Inactive
First Transmit
Edge
Receive
Edge
Transmit
Edge
Last Receive
Edge
t5
Data
valid
t4
Data
valid
t12
t13
Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.
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