參數(shù)資料
型號(hào)： SAF-XC2735X-72F80L
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PQFP64
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 33/101頁(yè)
文件大小： 862K
代理商： SAF-XC2735X-72F80L
XC2735X
XC2000 Family Derivatives / Base Line
Functional Description
Data Sheet
37
V2.0, 2009-03
3.7
Capture/Compare Unit (CAPCOM2)
The CAPCOM2 unit supports generation and control of timing sequences on up to
16 channels with a maximum resolution of one system clock cycle (eight cycles in
staggered mode). The CAPCOM2 unit is typically used to handle high-speed I/O tasks
such as pulse and waveform generation, pulse width modulation (PWM), digital to
analog (D/A) conversion, software timing, or time recording with respect to external
events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for
the capture/compare register array.
The input clock for the timers is programmable to a number of prescaled values of the
internal system clock. It may also be derived from an overflow/underflow of timer T6 in
module GPT2. This provides a wide range for the timer period and resolution while
allowing precise adjustments for application-specific requirements. An external count
input for CAPCOM2 timer T7 allows event scheduling for the capture/compare registers
with respect to external events.
The capture/compare register array contains 16 dual purpose capture/compare
registers. Each may be individually allocated to either CAPCOM2 timer T7 or T8 and
programmed for a capture or compare function.
Each register of the CAPCOM2 module has one port pin associated with it.A port pin is
associated with 8 registers of the CAPCOM2 module. This serves as an input pin to
trigger the capture function or as an output pin to indicate the occurrence of a compare
event.
Table 9
Compare Modes (CAPCOM2)
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
Several compare interrupts per timer period are possible
Mode 1
Pin toggles on each compare match;
Several compare events per timer period are possible
Mode 2
Interrupt-only compare mode;
Only one compare interrupt per timer period is generated
Mode 3
Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
Only one compare event per timer period is generated
Double Register
Mode
Two registers operate on one pin;
Pin toggles on each compare match;
Several compare events per timer period are possible
Single Event Mode
Generates single edges or pulses;
Can be used with any compare mode
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