參數(shù)資料
型號： SAF-XC2735X-72F80L
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PQFP64
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-64
文件頁數(shù)： 20/101頁
文件大?。?/td> 862K
代理商： SAF-XC2735X-72F80L
XC2735X
XC2000 Family Derivatives / Base Line
Functional Description
Data Sheet
25
V2.0, 2009-03
Up to 32 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code
or data. The PSRAM is accessed via the PMU and is optimized for code fetches. A
section of the PSRAM with programmable size can be write-protected.
Note: The actual size of the PSRAM depends on the quoted device type.
16 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data.
The DSRAM is accessed via a separate interface and is optimized for data access.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined
variables, for the system stack, and for general purpose register banks. A register bank
can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7,
RH7) General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR,
any location in the DPRAM is bit addressable.
Reserved
20’C000H
20’FFFFH
16 Kbytes
–
MultiCAN/USIC regs.
20’8000H
20’BFFFH
16 Kbytes
Alternate location4)
Reserved
20’6000H
20’7FFFH
8 Kbytes
–
USIC registers
20’4000H
20’5FFFH
8 Kbytes
Accessed via EBC
MultiCAN registers
20’0000H
20’3FFFH
16 Kbytes
Accessed via EBC
External memory area
01’0000H
1F’FFFFH
< 2 Mbytes
Minus segment 0
SFR area
00’FE00H
00’FFFFH
0.5 Kbyte
–
Dual-Port RAM
00’F600H
00’FDFFH
2 Kbytes
–
Reserved for DPRAM
00’F200H
00’F5FFH
1 Kbyte
–
ESFR area
00’F000H
00’F1FFH
0.5 Kbyte
–
XSFR area
00’E000H
00’EFFFH
4 Kbytes
–
Data SRAM
00’A000H
00’DFFFH
16 Kbytes
–
Reserved for DSRAM
00’8000H
00’9FFFH
8 Kbytes
–
External memory area
00’0000H
00’7FFFH
32 Kbytes
–
1) The areas marked with “<” are slightly smaller than indicated. See column “Notes”.
2) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH).
3) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
4) The alternate location for USIC and MultiCAN registers allows access to these modules using the same data
page pointer.
Table 6
XC2735X Memory Map (cont’d)
Address Area
Start Loc. End Loc.
Area Size1)
Notes
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