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| 型號： | SAF-XC2735X-72F80L |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 0.50 MM PITCH, GREEN, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 18/101頁 |
| 文件大?。?/td> | 862K |
| 代理商： | SAF-XC2735X-72F80L |
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XC2735X
XC2000 Family Derivatives / Base Line
Functional Description
Data Sheet
23
V2.0, 2009-03
3
Functional Description
The architecture of the XC2735X combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 3). This bus structure enhances overall system performance by
enabling the concurrent operation of several subsystems of the XC2735X.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XC2735X.
Figure 3
Block Diagram
Multi
CAN
DPRAM
CPU
PM
U
DM
U
BRGen
ADC1
8-Bit
10-Bit
RTC
MCHK
Interrupt& PEC
EBC
LXBus Control
External Bus
Control
DSRAM
PSRAM
System Functions
Clock, Reset, Power
Control, StandBy RAM
OCDS
Debug Support
Interrupt Bus
Pe
ri
ph
er
a
lD
at
a
B
u
s
Analog and Digital General Purpose IO (GPIO) Ports
MC_XY_BLOCKDIAGRAM
Flash Memory
GPT
T6
T5
T4
T3
T2
ADC0
8-Bit
10-Bit
CC2
T8
T7
LXBus
IM
B
WDT
CCU6x
T13
T12
USIC0
2 Ch.,
64 x
Buffer
RS232,
LIN,
SPI,
IIC , IIS
MAC Unit
MPU
CCU60
T13
T12
..
USICx
2 Ch.,
64 x
Buffer
RS232,
LIN,
SPI,
IIC, IIS
..
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