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參數資料
| 型號： | SAA7325 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數模轉換器（DAC）的數字伺服處理器和光盤譯碼器) |
| 中文描述： | 數字伺服處理器和光盤解碼器集成了援會（CD10型二）（具有綜合數模轉換器（DAC）的的數字伺服處理器和光盤譯碼器） |
| 文件頁數： | 9/68頁 |
| 文件大小： | 281K |
| 代理商： | SAA7325 |
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2000 Jun 26
9
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7325
7
FUNCTIONAL DESCRIPTION
7.1
Decoder part
7.1.1
P
RINCIPAL OPERATIONAL MODES OF THE DECODER
The decoding part supports a full audio specification at
single-speed (n = 1). A simplified data flow through the
decoder part is illustrated in Fig.7.
7.1.2
D
ECODING SPEED AND CRYSTAL FREQUENCY
The SAA7325 is a single-speed decoding device, with an
internalPhase-LockedLoop(PLL)clockmultiplierallowing
a choice of different crystals and oscillators to be used
(see Section 7.2). The range of crystal and oscillator
frequencies possible is controlled via decoder register B
and shown in Table 1. The MSB of decoder register B
must be set to logic 0.
The internal clock multiplier is controlled by SELPLL, and
should only be used if a 8.4672 or 16.9344 MHz crystal,
ceramic resonator or external clock is present.
7.1.3
L
OCK
-
TO
-
DISC MODE
Although nominally a single-speed device, for electronic
shock absorption applications the SAA7325 can be put
into lock-to-disc mode. This allows Constant Angular
Velocity (CAV) disc playback with varying input data rates
from the inside-to-outside of the disc. In the lock-to-disc
mode, the FIFO is blocked and the decoder will adjust its
output data rate to the disc speed. Hence, the frequency of
the I
2
S-bus (WCLK and SCLK) clocks are dependent on
the disc speed. In the lock-to-disc mode there is a limit on
the maximum variation in disc speed that the SAA7325 will
follow.
Disc speeds must always be within 25% to 100% range of
their nominal value. The lock-to-disc mode is
enabled/disabled by decoder register E.
7.1.4
S
TANDBY MODES
The SAA7325 may be placed in two standby modes
selected by decoder register B (it should be noted that the
device core is still active):
Standby 1: ‘CD-STOP’ mode; most I/O functions are
switched off
Standby 2: ‘CD-PAUSE’ mode; audio output features
are switched off, but the motor loop, the motor output
and the subcode interfaces remain active; this is also
called a ‘Hot Pause’.
In the standby modes the various pins will have the
following values:
MOTO1 and MOTO2: put in high-impedance, PWM
mode (standby 1 and reset: operating in standby 2); put
in high-impedance, PDM mode (standby 1 and reset:
operating in standby 2)
SCL and SDA: no interaction; normal operation
continues
SCLK, WCLK, DATA, EF and DOBM: 3-state in both
standby modes; normal operation continues after reset
CRIN, CROUT, CL16 and CL11/4: no interaction;
normal operation continues
V1, V2/V3, V4, V5 and CFLG: no interaction; normal
operation continues.
Table 1
Operating frequencies
Notes
1.
2.
The MSB of register B
must
be held at 0 (i.e. 0XXX).
The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0. CL11 is
available on the CL11/4 output, enabled by programming shadow register 3 (see Section 7.15.3).
REGISTER B
(1)
SELPLL
CRYSTAL FREQUENCY (MHz)
CL11 FREQUENCY (MHz)
(2)
33.8688
√
16.9344
√
√
8.4672
√
00XX
00XX
01XX
01XX
0
1
0
1
11.2896
11.2896
5.6448
11.2896
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