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參數(shù)資料
| 型號(hào)： | SAA7325 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數(shù)模轉(zhuǎn)換器（DAC）的數(shù)字伺服處理器和光盤(pán)譯碼器) |
| 中文描述： | 數(shù)字伺服處理器和光盤(pán)解碼器集成了援會(huì)（CD10型二）（具有綜合數(shù)模轉(zhuǎn)換器（DAC）的的數(shù)字伺服處理器和光盤(pán)譯碼器） |
| 文件頁(yè)數(shù)： | 11/68頁(yè) |
| 文件大?。?/td> | 281K |
| 代理商： | SAA7325 |
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2000 Jun 26
11
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7325
Fig.6 Data slicer showing typical application components.
47 pF
HFREF
HFIN
ISLICE
22 k
2.2 k
100 nF
100 nF
1 nF
HF input
crystal
clock
D
Q
DPLL
VSSA
VSSA
VSS
MGS179
VDD
100
μ
A
100
μ
A
7.4
Demodulator
7.4.1
F
RAME SYNC PROTECTION
A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data.
The master counter is only reset if:
A sync coincidence is detected; sync pattern occurs
588
±
1 EFM clocks after the previous sync pattern
A new sync pattern is detected within
±
6 EFM clocks of
its expected position.
The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence found, and reset LOW if during 61
consecutive frames no sync coincidence is found.
The PLL lock signal can be accessed via the SDA or
STATUS pins selected by decoder registers 2 and 7.
Also incorporated in the demodulator is a Run Length 2
(RL2) correction circuit. Every symbol detected as RL2 will
be pushed back to RL3. To do this, the phase error of both
edges of the RL2 symbol are compared and the correction
is executed at the side with the highest error probability.
7.4.2
EFM
DEMODULATION
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
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