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參數(shù)資料
| 型號： | SAA7325 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數(shù)模轉(zhuǎn)換器（DAC）的數(shù)字伺服處理器和光盤譯碼器) |
| 中文描述： | 數(shù)字伺服處理器和光盤解碼器集成了援會（CD10型二）（具有綜合數(shù)模轉(zhuǎn)換器（DAC）的的數(shù)字伺服處理器和光盤譯碼器） |
| 文件頁數(shù)： | 13/68頁 |
| 文件大?。?/td> | 281K |
| 代理商： | SAA7325 |
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2000 Jun 26
13
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7325
7.5
Subcode data processing
7.5.1
Q-
CHANNEL PROCESSING
The 96-bit Q-channel word is accumulated in an internal
buffer. The last 16 bits are used internally to perform a
Cyclic Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal will go LOW. SUBQREADY-I can
bereadviatheSDAorSTATUSpins,selectedviadecoder
register 2. Good Q-channel data may be read from SDA.
7.5.2
EIAJ 3
AND
4-
WIRE SUBCODE
(CD
GRAPHICS
)
INTERFACES
Data from all the subcode channels (P-to-W) may be read
via the subcode interface, which conforms to EIAJ
CP-2401. The interface is enabled and configured as
either a 3 or 4-wire interface via decoder register F.
The subcode interface output formats are illustrated in
Fig.8, where the RCK signal is supplied by another device
such as a CD graphics decoder.
7.5.3
V4
SUBCODE INTERFACE
Dataofsubcodechannels,Q-to-W,maybereadviapin V4
if selected via decoder register D. The format is similar to
RS232 and is illustrated in Fig.9. The subcode sync word
is formed by a pause of 200
μ
s minimum. Each subcode
byte starts with a logic 1 followed by 7 bits (Q-to-W).
The gap between bytes is variable between
11.3 and 90
μ
s.
The subcode data is also available in the EBU output
(DOBM) in a similar format.
Fig.8 EIAJ subcode (C graphics) interface format.
handbook, full pagewidth
SBSY
SFSY
RCK
SUB
SFSY
RCK
SUB
SFSY
RCK
SUB
EIAJ 4-wire subcode interface
EIAJ 3-wire subcode interface
SF0
SF1
SF2
SF3
SF97
SF0
SF1
P-W
P-W
P-W
P-W
P-W
P-W
P
Q
R
S
T
U
V
W
MBG410
SF0
SF1
SF2
SF3
SF97
SF0
SF1
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