參數(shù)資料
型號： SAA7325
廠商： NXP Semiconductors N.V.
英文描述： Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數(shù)模轉(zhuǎn)換器（DAC）的數(shù)字伺服處理器和光盤譯碼器)
中文描述： 數(shù)字伺服處理器和光盤解碼器集成了援會（CD10型二）（具有綜合數(shù)模轉(zhuǎn)換器（DAC）的的數(shù)字伺服處理器和光盤譯碼器）
文件頁數(shù)： 10/68頁
文件大小： 281K
代理商： SAA7325
2000 Jun 26
10
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7325
7.2
Crystal oscillator
The crystal oscillator is a conventional 2-pin design
operating between 8 and 35 MHz. This oscillator is
capable of operating with ceramic resonators and with
both fundamental and third overtone crystals. External
components should be used to suppress the fundamental
output of the third overtone crystals as shown in
Figs 3 and 4. Typical oscillation frequencies required are
8.4672, 16.9344 or 33.8688 MHz depending on the
internal clock settings used and whether or not the clock
multiplier is enabled (see Table 1).
7.3
Data slicer and clock regenerator
The SAA7325 has an integrated slice level comparator
which can be clocked by the crystal frequency clock, or
4 times the crystal frequency clock (if SELPLL is set HIGH
while using a 16.9344 MHz crystal and register 4 is set
to 0XXX), or 8 times the crystal frequency clock
(if SELPLL is set HIGH while using an 8.4672 MHz crystal,
and register 4 is set to 0XXX). The slice level is controlled
by an internal current source applied to an external
capacitor under the control of the Digital Phase-Locked
Loop (DPLL).
Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required and
the bit clock is not output. The PLL has two registers
(8 and 9) for selecting bandwidth and equalization.
The PLL response is shown in Fig.5.
For certain applications an off-track input is necessary.
This is internally connected from the servo part (its polarity
can be changed by the foc_parm1 parameter), but may be
input via the V1 pin if selected by register C. If this flag is
HIGH, the SAA7325 will assume that its servo part is
following on the wrong track, and will flag all incoming HF
data as incorrect.
Fig.3 8.4672 MHz fundamental configuration.
handbook, halfpage
OSCILLATOR
8.4672 MHz
CRIN
CROUT
SAA7325
33 pF
33 pF
MGL694
Fig.4 33.8688 MHz overtone configuration.
handbook, halfpage
OSCILLATOR
33.8688 MHz
CRIN
CROUT
SAA7325
3.3
μ
H
1 nF
10 pF
10 pF
MGL695
Fig.5 Digital PLL loop response.
1, 2 and 3 are all programmable via decoder register 8.
MGS178
handbook, halfpage
f
3
. PLL, LPF
2
. PLL bandwidth
1
. PLL integrator
PLL
loop
response
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