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參數(shù)資料
| 型號： | SAA7325 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數(shù)模轉換器（DAC）的數(shù)字伺服處理器和光盤譯碼器) |
| 中文描述： | 數(shù)字伺服處理器和光盤解碼器集成了援會（CD10型二）（具有綜合數(shù)模轉換器（DAC）的的數(shù)字伺服處理器和光盤譯碼器） |
| 文件頁數(shù)： | 16/68頁 |
| 文件大小： | 281K |
| 代理商： | SAA7325 |
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2000 Jun 26
16
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7325
7.7.4
M
UTE
,
FULL
-
SCALE
,
ATTENUATION AND FADE
A digital level controller is present on the SAA7325 which
performs the functions of soft mute, full-scale, attenuation
and fade; these are selected via decoder register 0:
Mute: signal reduced to 0 in a maximum of 128 steps;
3 ms
Attenuate: signal scaled by
12 dB
Full-scale: ramp signal back to 0 dB level; from mute
takes 3 ms
Fade: activates a 128 stage counter which allows the
signal to be scaled up/down by 0.07 dB steps
– 128 = full-scale
– 120 =
0.5 dB (i.e. full-scale if oversampling filter
used)
– 32 =
12 dB
– 0 = mute.
7.7.5
P
EAK DETECTOR
The peak detector measures the highest audio level
(absolute value) on positive peaks for left and right
channels. The 8 most significant bits are output in the
Q-channel data in place of the CRC bits. Bits 81 to 88
contain the left peak value (bit 88 = MSB) and
bits 89 to 96 contain the right peak value (bit 96 = MSB).
The values are reset after reading Q-channel data via
SDA.
Fig.11 Concealment mechanism.
Interpolation
Hold
Interpolation
MGA372
OK
Error
OK
Error
Error
Error
OK
OK
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