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參數(shù)資料
| 型號： | SAA7188A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital Video Encoder (DENC2-M)(數(shù)字視頻編碼器(DENC2-M)) |
| 中文描述： | 數(shù)字視頻編碼器（DENC2米）（數(shù)字視頻編碼器（DENC2米）） |
| 文件頁數(shù)： | 5/36頁 |
| 文件大小： | 252K |
| 代理商： | SAA7188A |
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1996 Jul 08
5
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2-M)
SAA7188A
LLC
38
Line-Locked Clock. This is the 27 MHz master clock for the encoder. The direction is set by
the CDIR pin.
Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals.
Crystal oscillator output (to crystal).
Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected
to ground.
digital ground 6
Real Time Control Input. If the clock is provided by an SAA7151B, RTCI should be connected
to the RTCO pin of the decoder to improve the signal quality.
Test pin. Connect to digital ground for normal operation.
Test pin. Connect to digital ground for normal operation.
Lower reference voltage input for the DACs.
Upper reference voltage input for the DACs.
Analog positive supply voltage 1 for the DACs and output amplifiers.
Analog output of the chrominance signal.
Analog supply voltage 2 for the DACs and output amplifiers.
Analog output of the luminance signal.
Analog ground for the DACs and output amplifiers.
Analog output of the CVBS signal.
Analog supply voltage 3 for the DACs and output amplifiers.
Current input for the output amplifiers, connect via a 15 k
resistor to V
DDA
.
Analog supply voltage 4 for the DACs and output amplifiers.
Reset input, active LOW. After reset is applied, all outputs are in 3-state input mode.
The I
2
C-bus receiver waits for the start condition.
Data acknowledge output of the parallel MPU interface, active LOW, otherwise high
impedance.
If pin 68 (SEL_MPU) is HIGH, this is the read/write signal of the parallel MPU interface,
otherwise it is the I
2
C-bus serial clock input.
If pin 68 (SEL_MPU) is HIGH, this is the address signal of the parallel MPU interface,
otherwise it is the I
2
C-bus serial data input/output.
If pin 68 (SEL_MPU) is HIGH, this is the chip select signal of the parallel MPU interface,
otherwise it is the I
2
C-bus slave address select pin. LOW: slave address = 88h, HIGH = 8Ch.
digital ground 7
CREF
XTALO
XTALI
39
40
41
V
SSD6
RTCI
42
43
AP
SP
V
refL
V
refH
V
DDA1
CHROMA
V
DDA2
Y
V
SSA
CVBS
V
DDA3
I
I
V
DDA4
RESET
44
45
46
47
48
49
50
51
52
53
54
55
56
57
DTACK
58
RW/SCL
59
A0/SDA
60
CS/SA
61
V
SSD7
DP0
DP1
DP2
DP3
V
DDD3
SEL_MPU
62
63
64
65
66
67
68
Lower 4 bits of the Data Port. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the parallel
MPU interface. If it is LOW, they are the UV lines of the Video Port.
digital supply voltage 3
Select MPU interface input. If it is HIGH, the parallel MPU interface is active, otherwise the
I
2
C-bus interface will be used.
SYMBOL
PIN
DESCRIPTION
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