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參數(shù)資料
| 型號(hào)： | S71GL128NC0BAWAZ0 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA84 |
| 封裝： | 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE COMPLIANT, FBGA-84 |
| 文件頁(yè)數(shù)： | 9/122頁(yè) |
| 文件大?。?/td> | 1764K |
| 代理商： | S71GL128NC0BAWAZ0 |
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106
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
Advan ce
In form ati o n
Power Down Program Sequence
The program requires 6 read/write operations with a unique address. Between
each read/write operation requires that device be in standby mode. The following
table shows the detail sequence.
The first cycle reads from the most significant address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle.
If the second or third cycle is written into the different address, the program is
cancelled, and the data written by the second or third cycle is valid as a normal
write operation.
The fourth and fifth cycles write to MSB. The data from the fourth and fifth cycles
is “don’t care.” If the fourth or fifth cycles are written into different address, the
program is also cancelled but write data might not be written as normal write
operation.
The last cycle is to read from specific address key for mode selection.
Once this program sequence is performed from a Partial mode to the other Partial
mode, the written data stored in memory cell array can be lost. So, it should per-
form this program prior to regular read/write operation if Partial mode is used.
Address Key
The address key has following format.
Cycle #
Operation
Address
Data
1st
Read
3FFFFFh (MSB)
Read Data (RDa)
2nd
Write
3FFFFFh
RDa
3rd
Write
3FFFFFh
RDa
4th
Write
3FFFFFh
Don’t Care (X)
5th
Write
3FFFFFh
X
6th
Read
Address Key
Read Data (RDb)
Mode
Address
32M
64M
A21
A20
A19
A18 - A0
Binary
Sleep (default)
1
3FFFFFh
4M Partial
N/A
1
0
1
37FFFFh
8M Partial
1
0
1
2FFFFFh
N/A
16M Partial
1
0
1
27FFFFh
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