參數(shù)資料
型號： S71GL128NC0BAWAZ0
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA84
封裝： 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE COMPLIANT, FBGA-84
文件頁數(shù)： 40/122頁
文件大?。?/td> 1764K
代理商： S71GL128NC0BAWAZ0
24
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
Advan ce
In form ati o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5V, X = Don’t Care, SA = Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are AMax:A0 in word mode. Sector addresses are AMax:A16 in both modes.
2. If WP# = VIL, the first or last sector group remains protected. If WP# = VIH, the first or last sector will be
protected or unprotected as determined by the method described in “Write Protect (WP#)”. All sectors are
unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending
on version ordered.)
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2, Figure 4, and
VersatileIOTM (VIO) Control
The VersatileIOTM (VIO) control allows the host system to set the voltage levels
that the device generates and tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. See Ordering Information for VIO options on this
device.
For example, a VI/O of 1.65 V to 3.6 V allows for I/O at the 1.8 or 3 volt levels,
driving and receiving signals to and from other 1.8-V or 3-V devices on the same
data bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to VIL. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
Operation
CE#
OE#
WE#
RESET#
WP#/
ACC
Addresses
(Note 1)
DQ0–DQ15
Read
L
H
X
AIN
DOUT
Write (Program/Erase)
L
H
L
H
Note 2
AIN
(Note 3)
Accelerated Program
L
H
L
H
VHH
AIN
(Note 3)
Standby
VCC ± 0.3 V
X
VCC ±
0.3 V
H
X
High-Z
Output Disable
L
H
X
High-Z
Reset
X
L
X
High-Z
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