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參數(shù)資料
| 型號： | S29GL128N11FFIVH2 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 110 ns, PBGA64 |
| 封裝： | 10 X 13 MM, 1 MM PITCH, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 6/74頁 |
| 文件大?。?/td> | 1593K |
| 代理商： | S29GL128N11FFIVH2 |
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12
S29GL-N
S29GL-N_01_A0 May 1, 2006
Da ta
Sh e e t
8.3
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See Reading Array Data on page 34 for more information. Refer to Read-Only Operations on page 59 for
timing specifications and to Figure 18.1 on page 59 for the timing diagram. Refer to DC Characteristics
on page 57 for the active current specification on reading array data.
8.3.1
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access speed for random locations within a page. The page size of
the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A(max)–A3.
Address bits A2–A0 in word mode (A2–A-1 in byte mode) determine the specific word within a page. This is
an asynchronous operation; the microprocessor supplies the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the
locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is de-
asserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses
are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses.
8.4
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The
“Word Program Command Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 8.3 on page 20 and
Table 8.4 on page 23 indicate the address space that each sector occupies.
Refer to DC Characteristics on page 57 table for the active current specification for the write mode.
AC Characteristics on page 59 contains timing specification tables and timing diagrams for write operations.
8.4.1
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming time than the standard programming algorithms. See
Write Buffer on page 12 for more information.
8.4.2
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at
the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce
the time required for program operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal
operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated
programming, or device damage may result. WP# has an internal pull-up; when unconnected, WP# is at VIH.
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