參數(shù)資料
型號： S29GL128N11FFIVH2
廠商： SPANSION LLC
元件分類： PROM
英文描述： 16M X 16 FLASH 3V PROM, 110 ns, PBGA64
封裝： 10 X 13 MM, 1 MM PITCH, LEAD FREE, FBGA-64
文件頁數(shù)： 27/74頁
文件大?。?/td> 1593K
代理商： S29GL128N11FFIVH2
May 1, 2006 S29GL-N_01_A0
S29GL-N
31
Data
She e t
9.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data. The system can read CFI information at the addresses
given in Table 9.1 to Table 9.3 on page 32. To terminate reading CFI data, the system must write the reset
command.
The system can also write the CFI query command when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read CFI data at the addresses given in Table 9.1 to
Table 9.4 on page 33. The system must write the reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact your sales representative for copies of
these documents.
Table 9.1 CFI Query Identification String
Addresses (x16)
Addresses (x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Table 9.2 System Interface String
Addresses (x16)
Addresses (x8)
Data
Description
1Bh
36h
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
38h
0036h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
3Ah
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
3Ch
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
3Eh
0007h
Typical timeout per single byte/word write 2
N s
20h
40h
0007h
Typical timeout for Min. size buffer write 2
N
s (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2
N ms (00h = not supported)
23h
46h
0003h
Max. timeout for byte/word write 2
N times typical
24h
48h
0005h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2
N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2
N times typical (00h = not supported)
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