
Epson Research and Development
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Vancouver Design Center
Hardware Functional Specification
S1D13A05
Issue Date: 02/07/02
X40A-A-001-02
7.2 Clock Selection
The following diagram provides a logical representation of the S1D13A05 internal clocks
used for the LCD controller.
Figure 7-1: Clock Selection
Note
1 CNF6 must be set at RESET#.
CLKI
CLKI2
÷2
0
1
BCLK
÷2
÷3
÷4
00
01
10
11
MCLK
00
01
10
11
÷2
÷3
÷4
000
001
010
011
÷8
1xx
PCLK
PWMCLK
REG[08h] bits 1,0
REG[70h] bits 2-1
REG[08h] bits 6-4
REG[04h] bits 5-4
CNF61
00
01
10
11
0
1
REG[04h] bit 0