Page 114
Epson Research and Development
Vancouver Design Center
S1D13A05
Hardware Functional Specification
X40A-A-001-02
Issue Date: 02/07/02
bits 9-0
FPLINE Pulse Start Position Bits [9:0]
These bits specify the start position of the horizontal sync signal, in 1 pixel resolution.
FPLINE Pulse Start Position in pixels = (REG[2Ch] bits 9-0) + 1
Note
For passive panels, these bits must be programmed such that the following formula is
valid.
HPW + HPS < HT
Note
bits 9-0
Vertical Total Bits [9:0]
These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical
Total is the sum of the Vertical Display Period and the Vertical Non-Display Period. The
maximum Vertical Total is 1024 lines.
REG[30h] bits 9:0 = Vertical Total in number of lines - 1
Note
1 This register must be programmed such that the following formula is valid.
VT > VDPS + VDP
2 If an HR-TFT panel is selected, the following formula must also apply.
VT > (REG[B8h] bits 2-0) + VDP + VPS + 1
bits 9-0
Vertical Display Period Bits [9:0]
These bits specify the LCD panel Vertical Display period, in 1 line resolution. The
Vertical Display period should be less than the Vertical Total to allow for a sufficient
Vertical Non-Display period.
REG[34h] bits 9:0 = Vertical Display Period in number of lines - 1
Vertical Total Register
REG[30h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
Vertical Total bits 9-0
15
14
13
12
11
10
9
87654
3210
Vertical Display Period Register
REG[34h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
Vertical Display Period bits 9-0
15
14
13
12
11
10
9
87654
3210
