參數(shù)資料
型號: S1C63408F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP128
封裝: PLASTIC, QFP-128
文件頁數(shù): 81/151頁
文件大?。?/td> 1171K
代理商: S1C63408F0A0100
S1C63406/408 TECHNICAL MANUAL
EPSON
27
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.3 OSC3 oscillation circuit
The S1C63406/408 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 4.2
MHz) for high speed operation and the source clock for peripheral circuits needing a high speed clock
(programmable timer, FOUT output). The mask option enables selection of CR, crystal or ceramic oscilla-
tion circuit.
This circuit operates with the VD1 voltage and the voltage level must be switched when the OSC3 oscilla-
tion is turned ON and OFF (see the next section for details).
Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit.
C CR
OSC3
OSC4
R
CR2
VSS
CGC
CDC
Ceramic/
X'tal2
OSC4
OSC3
R
RDC
FC
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
(a) CR oscillation circuit
(b) Ceramic/cryctal oscillation circuit
Fig. 4.3.3.1 OSC3 oscillation circuit
As shown in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the resistor
RCR2 between the OSC3 and OSC4 terminals when CR oscillation is selected. See Chapter 7, "Electrical
Characteristics", for resistance value of RCR2.
When crystal or ceramic oscillation is selected, the crystal or ceramic oscillation circuit can be configured
by connecting a crystal or ceramic oscillator (Max. 4.2 MHz) between the OSC3 and OSC4 terminals,
capacitor CGC between the OSC3 and OSC4 terminals, and capacitor CDC between the OSC4 and VSS
terminals. See Chapter 7, "Electrical Characteristics", for capacitor values of CGC and CDC. To reduce
current consumption of the OSC3 oscillation circuit, oscillation can be stopped by the software (OSCC
register).
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