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| 型號： | S1C63408F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 8/151頁 |
| 文件大小： | 1171K |
| 代理商： | S1C63408F0A0100 |
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S1C63406/408 TECHNICAL MANUAL
EPSON
97
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
RXEN: Receive enable register (FF72HD2)
Sets the serial interface to the receive enabled status.
When "1" is written: Receive enabled
When "0" is written: Receive disabled
Reading: Valid
When "1" is written to RXEN, the serial interface shifts to the receive enabled status and shifts to the
receive disabled status when "0" is written.
Set RXEN to "0" when making the initial settings of the serial interface and similar operations.
At initial reset, this register is set to "0".
RXTRG: Receive trigger/status (FF72HD3)
Functions as the receive start trigger or preparation for the following data receiving and the operation
status indicator (during receiving/during stop).
When "1" is read: During receiving
When "0" is read: During stop
When "1" is written: Start receiving/following data receiving preparation
When "0" is written: Invalid
RXTRG has a slightly different operation in the clock synchronous system and the asynchronous system.
The RXTRG in the clock synchronous system is used as the trigger for starting receive operation.
Write "1" into RXTRG to start receiving at the point where the receive data has been read and the
following receive preparation has been done. (In the slave mode, SRDY becomes "0" at the point where
"1" has been written into into the RXTRG.)
In the asynchronous system, RXTRG is used for preparation of the following data receiving. Read the
received data located in the receive data buffer and write "1" into RXTRG to inform that the receive data
buffer has shifted to empty. When "1" has not been written to RXTRG, the overrun error flag OER is set to
"1" at the point where the following receiving has been completed. (When the receiving has been com-
pleted between the operation to read the received data and the operation to write "1" into RXTRG, an
overrun error occurs.)
In addition, RXTRG can be read as the status. In either clock synchronous mode or asynchronous mode,
when RXTRG is set to "1", it indicates receiving operation and when set to "0", it indicates that receiving
has stopped.
At initial reset, RXTRG is set to "0".
TRXD0–TRXD7: Transmit/receive data (FF74H, FF75H)
During transmitting
Transmitting data is set.
When "1" is written: High level
When "0" is written: Low level
Write the transmitting data prior to starting transmition.
In the case of continuous transmitting, wait for the transmit completion interrupt, then write the data.
The TRXD7 becomes invalid for the 7-bit asynchronous mode.
Converted serial data for which the bits set at "1" as High (VDD) level and for which the bits set at "0" as
Low (VSS) level are output from the SOUT terminal.
During receiving
The received data is stored.
When "1" is read: High level
When "0" is read: Low level
The data from the receive data buffer can be read out.
Since the sift register is provided separately from this buffer, reading can be done during a receive opera-
tion in the asynchronous mode. (The buffer function is not used in the clock synchronous mode.)
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