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參數(shù)資料
| 型號(hào)： | S1C63408F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 16/151頁 |
| 文件大?。?/td> | 1171K |
| 代理商： | S1C63408F0A0100 |
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104
EPSON
S1C63406/408 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
4.14 Interrupt and HALT/SLEEP
<Interrupt types>
The S1C63406/408 provides the following interrupt functions.
External interrupt: Input port interrupt
(4 systems)
Internal interrupt: Watchdog timer interrupt
(NMI, 1 system)
Programmable timer interrupt
(2 systems)
Serial interface interrupt
(3 systems)
Timer interrupt
(4 systems)
Stopwatch timer interrupt
(2 systems)
To authorize interrupt, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask
registers must be set to "1" (enable).
When an interrupt occurs the interrupt flag is automatically reset to "0" (DI), and interrupts after that are
inhibited.
The watchdog timer interrupt is an NMI (non-maskable interrupt), therefore, the interrupt is generated
regardless of the interrupt flag setting. Also the interrupt mask register is not provided. However, it is
possible to not generate NMI since software can stop the watchdog timer operation.
Figure 4.14.1 shows the configuration of the interrupt circuit.
Note: After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of
them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the
other one is set.
<HALT/SLEEP>
The S1C63406/408 has HALT and SLEEP functions that considerably reduce current consumption when
it is not necessary.
The CPU enters HALT status when the HALT instruction is executed.
In HALT status, the operation of the CPU is stopped. However, timers continue counting since the
oscillation circuit operates. Reactivating the CPU from HALT status is done by generating a hardware
interrupt request including NMI.
When the CPU enters SLEEP status as the result of the SLP instruction, the CPU stops its operation, the
OSC3 oscillation circuit and supplying the OSC1 clock to the divider and peripheral circuits. However,
the OSC1 oscillation circuit does not stop its oscillation.
Reactivating from SLEEP status can only be done by generation of an input port interrupt factor. There-
fore, set the following flag and the registers for the K0x port to be used to cancel SLEEP status before
executing the SLP instruction.
Interrupt flag (I flag) = "1" (interrupts are enabled)
Interrupt selection register SIK0x = "1" (the K0x input port interrupt is selected)
Interrupt mask register EIK0x = "1" (the K0x input port interrupt is enabled)
Noise rejector selection register K0NR1–K0NR0 = "00" (noise rejector is bypassed)
When SLEEP status is canceled by an input interrupt, wait for oscillation to stabilize, then restart the CPU
operation (input port interrupt processing).
Refer to the "S1C63000 Core CPU Manual" for transition to the HALT/SLEEP status and timing of its
cancellation.
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