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參數(shù)資料
| 型號： | S1C60N01F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | PLASTIC, QFP12-48 |
| 文件頁數(shù)： | 48/153頁 |
| 文件大小： | 901K |
| 代理商： | S1C60N01F |
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S1C60N01 TECHNICAL SOFTWARE
EPSON
II-53
CHAPTER 4: SUMMARY OF PROGRAMMING POINTS
Interrupt
– Re-start from the HALT state is performed by the inter-
rupt. The return address after completion of the interrupt
processing in this case will be the address following the
HALT instruction.
– When interrupt occurs, the interrupt flag will be reset by
the hardware and it will become DI state. After comple-
tion of the interrupt processing, set to the EI state
through the software as needed.
Moreover, the nesting level may be set to be program-
mable by setting to the EI state at the beginning of the
interrupt processing routine.
– Be sure to reset the interrupt factor flag before setting to
the EI state on the interrupt processing routine. The
interrupt factor flag is reset by reading through the
software. Not resetting the interrupt factor flag and
interrupt mask register being "1", will cause the same
interrupt to occur again.
– The interrupt factor flag will be reset by reading through
the software. Because of this, when multiple interrupt
factor flags are to be assigned to the same address,
perform the flag check after the contents of the address
has been stored in the RAM. Direct checking with the
FAN instruction will cause all the interrupt factor flag to
be reset.
– Reading of interrupt factor flags is available at EI, but be
careful in the following cases.
If the interrupt mask register value corresponding to the
interrupt factor flags to be read is set to "1", an interrupt
request will be generated by the interrupt factor flags set
timing, or an interrupt request will not be generated.
Vacant Register and
Read/Write
Writing data into the addresses where read/write bits
and read only bits are mixed in 1 word (4 bits) does not
affect the read only bits.
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