參數(shù)資料
型號(hào): S1C60N01F
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP48
封裝: PLASTIC, QFP12-48
文件頁(yè)數(shù): 117/153頁(yè)
文件大?。?/td> 901K
代理商: S1C60N01F
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I-54
EPSON
S1C60N01 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
When an interrupt request is input to the CPU, the CPU
begins interrupt processing. After the program being exe-
cuted is suspended, interrupt processing is executed in the
following order:
The address data (value of the program counter) of the
program step to be executed next is saved on the stack
(RAM).
The interrupt request causes the value of the interrupt
vector (page 1, 01H–07H) to be loaded into the program
counter.
The program at the specified address is executed (execu-
tion of interrupt processing routine).
The processing in steps 1 and 2, above, takes 12 cycles of the
CPU system clock.
Interrupt vectors
Note
The interrupt factor flags can be masked by the correspond-
ing interrupt mask registers. The interrupt mask registers
are read/write registers. They are enabled (interrupt en-
abled) when 1 is written to them, and masked (interrupt
disabled) when 0 is written to them. After an initial reset,
the interrupt mask register is set to 0.
Table 4.9.2 shows the correspondence between interrupt
mask registers and interrupt factor flags.
Specific masks and
factor flags for inter-
rupt
Table 4.9.2
Interrupt mask registers and
interrupt factor flags
*
There is an interrupt mask register for each input port pin.
Interrupt Mask Register
EIT2
EIT8
EIT32
EIK03*
EIK02*
EIK01*
EIK00*
Interrupt Factor Flag
(0EBH D2)
(0EBH D1)
(0EBH D0)
(0E8H D3)
(0E8H D2)
(0E8H D1)
(0E8H D0)
IT2
IT8
IT32
(0EFH D2)
(0EFH D1)
(0EFH D0)
IK0
(0EDH D0)
相關(guān)PDF資料
PDF描述
S1C60N02D 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, UUC52
S1C60L02 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP60
S1C60N04D 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC48
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