參數(shù)資料
型號: S1C60N01F
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP48
封裝: PLASTIC, QFP12-48
文件頁數(shù): 145/153頁
文件大?。?/td> 901K
代理商: S1C60N01F
S1C60N01 TECHNICAL SOFTWARE
EPSON
II-3
CHAPTER 1: CONFIGURATION
Interrupt Vectors
When an interrupt request is received by the CPU, the CPU
initiates the following interrupt processing after completing
the instruction being executed.
(1) The address of the next instruction to be executed (the
value of the program counter) is saved on the stack
(RAM).
(2) The interrupt vector address corresponding to the inter-
rupt request is loaded into the program counter.
(3) The branch instruction written in the vector is executed
to branch to the software interrupt processing routine.
Steps 1 and 2 require 12 cycles of the CPU system clock.
The interrupt vectors are shown in Table 1.3.1.
1.3
Note
Table 1.3.1
Interrupt requests and vectors
Addesses (start address of interrupt processing routines) to
jump to are written into the addresses available for interrupt
vector allocation.
Step
Interrupt Vector
Initial reset
Clock timer interrupt
Input (K00–K03) interrupt
Input interrupt and clock timer interrupt
Page
00H
01H
04H
05H
1
相關(guān)PDF資料
PDF描述
S1C60N02D 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, UUC52
S1C60L02 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP60
S1C60N04D 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC48
S1C60N08D 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, UUC96
S1C60N08F0A0100 MICROCONTROLLER, PQFP100
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