參數(shù)資料
型號: RV5C386A-E2
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: I2C-bus Real-Time Clock ICs with Voltage Monitoring Function
中文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO10
封裝: 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10
文件頁數(shù): 34/42頁
文件大?。?/td> 362K
代理商: RV5C386A-E2
RV5C386A PRELIMINARY
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In the pulse mode, the increment of the second counter is delayed by approximately 92
μ
s from the falling edge of
clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag
behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will
reset the other time counters of less than 1 second, driving the /INTRA pin low.
*2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1
minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the
falling edge of periodic interrupt signals. For example, periodic interrupt signals with an
interrupt cycle setting of 1 second are output in synchronization with the increment of the second
counter as illustrated in the timing chart below.
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as follows:
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of
±
3.784ms. For
example, 1-Hz clock pulses will have a duty cycle of 50
±
0.3784%.
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of
±
3.784 ms.
32-kHz CLOCK OUTPUT
For the RV5C386A, 32.768-kHz clock pulses are output from the 32KOUT pin when the CLKC pin is set to
high. If CLKC is set to low or opened, the 32KOUT pin is driven low.
For the RV5C386A, the 32KOUT pin output is synchronized with CLKC pin input as illustrated in the timing
chart below.
/INTRA Pin
(Increment of
second counter)
CTFG Bit
Setting CTFG bit to 0
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
14.5.
32KOUT pin
CLKC pin
Max.76.3
μ
s
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